Recent improvements in the manufacture of high power solid state amplifiers have given rise to applications in new fields such as microwave cooking, ignition engine efficiency and in medical devices and treatments.
Conventionally, an RF heating apparatus such as a microwave oven generates RF power to be introduced into a cavity using the device known as a magnetron. A magnetron is an oscillator-amplifier that typically provides RF energy only at a single frequency (for example 2.5 GHz).
The efficiency of the heating provided by a microwave oven is dependent upon the proportion of the RF energy introduced into a cavity of the oven that is actually absorbed by the food or beverage being heated. Normally, at least some of the RF energy introduced into the cavity is reflected back to the magnetron, whereby the power efficiency of the heating apparatus is reduced. It is well known that the reflection of the RF energy inside the cavity depends on factors such as the wavelength, phase and amplitude of the RF radiation, the size, shape and cross section of the food or beverage, and the dimensions and shape of the cavity itself.
Accordingly, it is known that one way to optimise the amount of RF energy that is absorbed by the food or beverage being heated is to trim the physical parameters of the RF radiation, to minimise the reflected signal. These parameters include the amplitude, frequency and/or phase of the radiation. Although a magnetron is a relatively cheap component, it does not allow for this kind of trimming. On the other hand, solid state devices may be able to provide trimming since they can enable multi-frequency, multi-phase operation, with multiple paths.
FIG. 1 shows an example of an RF circuit 10 including solid state components that can be used to implement trimming of the kind noted above. The circuit 10 includes a plurality of paths A, B, C. Each path includes a phase locked loop (PLL) 2A, 2B, 2C for producing an RF signal. As shown by the dashed lines, the PLLs 2B and 2C may in some examples be disabled (or simply omitted), such that PLL 2A can be used to provide the RF signal for each path. In such examples, the PLL 2A is thus a common PLL that is shared by each path A, B, C, and each path A, B, C would typically operate at the same frequency (i.e. the operating frequency of the PLL 24). Where separate PLLs (e.g. 2A, 2B, 2C) are provided for each path, multi-frequency operation may be enabled.
An output of each PLL 2A, 2B, 2C (or, as noted above, the output of a common or shared PLL 2A) is connected to phase shifters 4A, 4B, 4C. The phase shifters 4A, 4B and 4C can be used to apply the phase shifts to the RF signal of each path under the control of a microcontroller 14. Accordingly, the microcontroller 14 may adjust the phase of each path for trimming the RF radiation produced by the system. Note that the microcontroller 14 may also control the PLLs 2A, 2B, 2C to adjust the frequency of the RF signal in each path A, B, C.
The phase shifted signals are then provided to variable gain amplifiers 6A, 6B, 6C and then to power amplifiers 8A, 8B, 8C for subsequent introduction of RF radiation into the cavity of the heating apparatus by respective antennae 12A, 12B, 12C.
When each path works at the same operating frequency, it is important for the phase between the paths to be accurate and not time varying. Typically, this property can only be achieved if one of the paths provides a phase reference (e.g. a reference signal used by PLL 2A) to each of the other paths so that it is possible to provide phase coherent signals to the phase shifters 4A, 4B, 4C on a local and individual basis without changing the global phase coherence.
FIG. 2 shows a frequency synthesiser 21 of the kind that is well known in the art. The frequency synthesiser includes a phase lock loop (PLL) having a voltage controlled oscillator 32 that receives a control signal from a phase frequency detector 26. The control signal provided by the phase frequency detector 26 is typically filtered by a low pass filter 28. The phase frequency detector 26 receives a reference frequency Fref that is produced by a crystal oscillator 22 (VCXO, TCXO, XO . . . etc). If required, the output of the crystal oscillator 22 may be adjusted by a divider 24 to produce the desired frequency of Fref. The phase frequency detector 26 also receives a feedback signal Fdiv from a divider 30 that divides the output of the voltage controlled oscillator 32. The control signal produced by the phase frequency detector 26 depends on the relative frequency and phases of the signals Fref and Fdiv.
The divider 30 can be an integer-N or a fractional-N divider for producing what are commonly known as integer-N phase lock loops or fractional-N phase lock loops, respectively. In either case, the divider 30 allows the output of the PLL (Fvco) to be a multiple of Fref (Fvco=N*Fref for an integer-N PLL or Fvco=(N+k/q)*Fref (where q>k) for a fractional-N PLL).
In some examples, the output of the frequency synthesiser 21 can be provided with a divider 34 which can be used to programmably tune the output frequency Fout (Fout=Fvco/P, where P is the modulus of the divider 34).
Each of FIGS. 3-5 illustrates examples of how multiple frequency synthesisers can be connected together to allow for the production of multiple RF signals of the kind described required by the arrangement of FIG. 1. In each case, a synchronisation signal can be distributed between the frequency synthesisers for synchronising the frequency and phase of their outputs. The synchronised outputs of the frequency synthesisers can then be used as a starting point for accurate phase trimming, for example in an RF heating apparatus.
In the example of FIG. 3, the RF circuit 20 includes two frequency synthesisers, each including a PLL of the kind noted above in relation to FIG. 2. The frequency synthesisers are both integer-N frequency synthesisers. In this example, each frequency synthesiser includes a divider 34A, 34B for programmably tuning the output frequency Fout1, Fout2 as described above. The second frequency synthesiser includes a phase shifter for trimming the output phase of the second frequency synthesiser relative to the output phase of the first frequency synthesiser e.g., in an RF heating apparatus).
In FIG. 3, it is shown that a synchronisation signal is distributed from the first frequency synthesiser to the second frequency synthesiser by simply connecting the output of the crystal oscillator 24 (which may be modified by divider 24) to the phase frequency detectors 26A and 26B of each PLL. The synchronisation signal has frequency Fref1 and phase φref1.
In the example of FIG. 3, there is a static phase shift between the outputs of the two frequency synthesisers (Fout1, φout1; Fout2, φout2). This can be deduced as follows:                phase φout1 is φvco1 plus the static delay of the divider 34A (where φvco1 is the phase of the output of the voltage controlled oscillator 32A of the first frequency synthesiser);        the phase at the output of the integer-N divider 30A φdiv1 is exactly φvco1/N;        the phase of the reference signal φref1 is φdiv1 the PLL is locked;        similarly, the phase at the output of the integer-N divider 30B φdiv2 is φref1 because the 2nd synthesizer is also locked;        the phase φvco2 of the output of the voltage controlled oscillator 32B of the second frequency synthesiser is exactly N*φdiv2;        the phase at the output of the divider 34B φout2_unshifted is φvco2 plus the static delay of the divider 34B; and        φout2 is φout2_unshifted plus the static phase inside the phase shifter 36.        
As a result, the difference in phase between φout1 and φout2 is not known precisely. Nevertheless, the phase difference is generally fixed and time invariant since a phase fluctuation at the output of the first frequency synthesizer will lead to the same phase fluctuation at the output of the second frequency synthesiser.
The example in FIG. 3 has a number of problems associated with it. Firstly, phase noise at the output of the first frequency synthesizer is not correlated to that of the second frequency synthesiser. This can result in jitter between the outputs. Secondly, a circuit using the layout of FIG. 3 must necessarily use integer-N frequency synthesisers because there is no simple, well defined relationship between the phases at the input and output of the divider (e.g. the dividers 30A, 30B in FIG. 3) in a fractional-N PLL. Because the use of an integer-N frequency synthesiser is mandatory, to allow for small changes in the output frequency, Fref1 needs to be small (Fvco=N*Fref). However, a smaller reference frequency is known to produce higher phase noise at the output, so that the arrangement in FIG. 3 is not suitable for low noise applications. It is further noted that integer-N frequency synthesisers tend to have a longer settling time at low frequencies.
In FIG. 4, a synchronisation signal is instead supplied directly from the output of the first frequency synthesiser. As such the dashed portions of the second frequency synthesiser may be disconnected using multiplexer 38 or simply omitted. The multiplexer 38 routes the synchronisation signal directly to the phase shifter 36 for production of a phase trimmed output having frequency Fout2 and phase φout2.
Because the synchronisation signal in this example is supplied from the output of the first frequency synthesiser, the only source of uncorrelated noise between each channel arises from the multiplexer 38 and the phase shifter 36. However, the arrangement in FIG. 4 also has a number of problems associated with it. In particular, at high frequencies (e.g. at RF frequencies), distribution of the synchronisation signal (which has the same frequency as the output frequency Fout1 of the first channel) becomes difficult due to attenuation and loss of frequency and/or phase integrity of the synchronisation signal. These difficulties are particularly troublesome where the physical distance between the channels is large (compared to the wavelength of the signal) so that relatively long distribution paths are required. This can impose unwanted restrictions on the design of, for example, an RF heating apparatus.
In FIG. 5, the arrangement of the channels is similar to that in FIG. 4. In cases where the phase shifter 36 needs an input that is 90° shifted with respect to the signal in the first channel to operate correctly, the divider 34A can be a 2/P divider (where P is an integer), and further dividers 40A and 40B can be provided, which are dividers by 2. In FIG. 5, the synchronisation frequency is even higher than the output frequency Fout1 of the first channel (e.g. twice), whereby the signal distribution problems noted above are exacerbated. Moreover, it is well known that at start up, dividers-by-2 begin with an unknown phase of +/−180°. This unknown factor means that the phase of the second channel can only be known to within +/−180°, which is generally not acceptable.